Multilayer ceramic chips 22 (FIG. 1) are common capacitors used for bypass, coupling, or energy storage applications in electronic circuits. The chips 22 include internal parallel plates 26 in dielectric body 28 such as a ceramic. The parallel plates are connected by terminations 24, 25 on the outer edges of the chip 22. End terminations 24, 25 electrically connect each of the respective internal electrode plates 26 and provide an external electrical connection to the multilayer capacitor. Common sizes of the chips may range from 0201 (0.02″×0.01″) to 1206 (0.12″×0.06″). Larger sized chips may give higher capacitance at any given voltage rating. In some cases, there may be a need for much larger multilayer ceramic capacitors, ranging in size from 0.25″×0.25″, up to 1.2″×1.2″ in area. Usually in these larger sizes, it is desirable to use multiple chips together. These chips 22 are often stacked one on top of another as illustrated in FIGS. 2A and 2B, then soldered 29 together with leads or are soldered to a lead frame 26. With this technique, it is possible to make large capacitance values (1 μF to 180 μF) at moderate voltages (50 V to 500V).
Stacked capacitors 20 may be used in different power supply designs including: (1) resonant power supplies, operating at 1 MHz to 60 MHz, with a high power AC sine wave applied to the capacitors; (2) direct filtering across three phases of an AC supply operating at low frequency (60-800 Hz) at moderate voltages (48-480 volts); and (3) DC-DC converters, on the input or output side of the supply, where the capacitors see a moderate DC voltage plus an AC ripple that comes off of a switching transistor (at 100k kHz to 500 kHz and 0.1 to 3 amps current). The stacked capacitors may carry high power due to high ripple current from switching transistors.
Circuit designers who use stacked capacitors 20 for these applications are concerned first with the capacitance and voltage rating that will make the circuit function. There is also a concern with second order effects such as the effects of heat dissipation affecting thermal expansion or contraction and vibration from mechanical shock. Heat dissipation is primarily achieved by conduction. It is generally accepted that air convection accounts for only a small portion of the heat dissipated from the chip 22. Conduction occurs through an internal electrode to the silver end terminations 24 through the solder 29 to the lead frames 26 and then into a circuit board 30 or other substrate. In the case of the stacked capacitor 20, the heat conduction has a longer path due to the height of the stack. Heat conduction from the top of the stack down to the circuit board 30 may be very inefficient.
Generally speaking, since a significant amount of heat is generated in the vicinity of a source, substrates are normally constituted with aluminum having a high heat discharge capacity. However, since the temperature in the vicinity of the source changes greatly when the source is turned on and off, a significant amount of thermal stress occurs at a ceramic capacitor mounted on the aluminum substrate, which has a high coefficient of thermal expansion. This thermal stress may cause cracking to occur at the ceramic capacitor, which, in turn, may induce problems such as shorting defects and arcing.
Further concerns about the performance of stacked capacitors arise under vibration and mechanical shock conditions. The stacks may be tall and heavy. Under normal design conditions, the height may reach 0.72 inches in some stacked configurations, with areas ranging from 0.25″×0.25″ up to 1.2″×2.0″. When used in a satellite or rocket, there is a legitimate concern of the part falling off of the circuit board, or at least of the solder joints cracking or breaking loose resulting from excessive vibrations and extreme environmental conditions. Many designers resort to using an epoxy to help adhere the capacitor to the board, but this is not optimal because the epoxy itself might cause problems, such as thermal stresses, under certain temperature conditions due to the expansion or contraction of the epoxy.
An additional concern is that the inductance of the capacitors in a power application may have a large impact on the performance of the chip. Lower inductance is always a good property in a ceramic capacitor. One common method of achieving lower inductance is to rotate the aspect ratio of the chip as can be seen in FIG. 2C. A traditional 1206 chip 22 (0.12″×0.06″), FIG. 1B, can have half the inductance if the dimensions of the chip 22 are changed to 0612 (0.06″×0.12″) as shown on chip 32, FIG. 2C. Literature claims that the change from 1206 to 0612 will reduce the inductance from 1200 pH to 170 pH.
Beam lead capacitors, such as the beam lead capacitor 40 of FIG. 3A and FIG. 3B, are typically composed of a single layer parallel plate capacitor 40 with the parallel plates 42 on either side of a dielectric 44 parallel to a circuit board 46 (FIG. 3C). Two silver foil leads 48, 50 electrically connect the capacitor to the circuit board 46. The bottom lead 48 is traditionally soldered to the circuit board 46 and the top lead 50 solders down to a different location on the board 46. One key aspect of the beam lead capacitor 40 is that the configuration of the capacitor was not intended to be soldered at the chip itself. Rather, the ribbon leads 48, 50 specifically exist to allow the part to be soldered away from the capacitor. This is done to either avoid thermal shock, or to allow connection to some other location away from the capacitor as seen, for example in FIG. 3C and FIG. 3D. The width of the top “beam” lead 50 may be the same width as a conductor on the circuit board 46. Because the beam lead arrangement does not contain interior plates, it does not benefit from the advantages of multilayer capacitors.
What is needed in the art, therefore, is a stacked multilayer capacitor that does not have the disadvantages described above.